Super small CPU cores are fantastic for complex FSM replacement, especially on an FPGA which has unused block RAMs (so using them is essentially free.)
I’ve seen cases with relatively complex pure HW FSM being replace by a small CPU and 1KB of RAM where the logic used by the CPU ends up smaller than the FSM.
But now the CPU is programmable, so you can iterate much quicker in case of bugs, without the need to reaunthesize.
A good example are SDRAM controllers: almost all of them have a small CPU inside the controller that is used for calibration training.
I’ve seen cases with relatively complex pure HW FSM being replace by a small CPU and 1KB of RAM where the logic used by the CPU ends up smaller than the FSM.
But now the CPU is programmable, so you can iterate much quicker in case of bugs, without the need to reaunthesize.
A good example are SDRAM controllers: almost all of them have a small CPU inside the controller that is used for calibration training.