RISC-V does not have carry and overflow flags in the traditional sense. Which is actually great because it needs you don't have to specify the complicated details of how any single instruction might affect the flags. (And yes, it uses compare-and-branch instructions instead.) It does provide suggested insn sequences to check for overflow, which might be executed as a single instruction in a more full-featured implementation.

Those sequences of instructions transform the cheapest arithmetic operations into very expensive operations and they make unachievable the concurrent execution of up to 8 arithmetic instructions, which is possible in other modern CPU cores.

Using instruction fusion of a pair of instructions to achieve the effect of indexed addressing, but in a many times more complex and more inefficient way, is believable even if ugly.

Using instruction fusion to fuse the long sequence needed for checking overflow into a single operation is unbelievable.

Even if that were done, the immense discrepancy in complexity between detecting overflow with one extra XOR gate in a 64-bit adder that may have hundreds of gates, depending on its speed, and an instruction decoder capable of fetching ahead and decoding the corresponding long instruction sequence into one micro-operation is ridiculous.